Nikiforov
Vladimir O.
D.Sc., Prof.
doi: 10.17586/2226-1494-2019-19-3-516-522
PARAMETRIC OPTIMIZATION OF DIGITAL INTEGRATED CIRCUITS FOR MICROMECHANICAL SENSORS
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Abstract
Subject of Research. The task of energy consumption reducing and energy efficiency improvement is one of the key ones when designing systems on a chip. The main parameters affecting power consumption are the clock frequency and supply voltage. Determination of these parameters values under given technological and time constraints is the main goal of optimization. The paper discusses the ways of energy efficiency assessment for digital integrated circuits. An optimization criterion for one of the architectures of digital blocks is derived. Method. A method for parametric optimization of digital integrated circuits for micromechanical sensors is proposed. The method gives the possibility to optimize the parameters of computing devices according to the criterion of minimum energy consumption. Main Results. The methodology approbation results are presented on the example of sequential and pipelined architectures of digital blocks. Practical Relevance. The proposed technique can be used in the development of digital integrated circuits for any manufacturing technology and provides the evaluation of the parameters for digital integrated circuits with their optimization in the given constraints.
Acknowledgements. This work was supported by the project No. 19-08-00052 of the Russian Foundation for Basic Research, Russian Federation.
References
2. Kealy A., Retscher G., Grejner-Brzezińska D., Gikas V., Roberts G. Evaluating the perfomance of MEMS based Inertial navigation sensors for land mobile application. Archives of Photogrammetry, Cartography and Remote Sensing, 2011, vol. 22, pp. 237–248.
3. Simunic T., Benini L., De Micheli G. Energy-efficient design of battery-powered embedded systems. Proc. Int. Symposium on Low Power Electronics and Design. San Diego, USA, 1999, pp. 212–217.
4. Agrawal P., Rao S. Energy-efficient scheduling: classification, bounds, and algorithms. arXiv, arXiv:1609.06430, 2016, 41 p.
5. Joy V.M., Krishnakumar S. Efficient load scheduling method for power management. International Journal of Scientific and Technology Research, 2016, vol. 5, pp. 99–101.
6. Suguna T., Janaki Rani M. Survey on power optimization techniques for low power VLSI circuit in deep submicron
technology. International Journal of VLSI design and Communication Systems, 2018, vol. 9, no. 1, pp. 1-15. doi: 10.5121/vlsic.2018.9101
7. Sharma N., Kaur M. A survey of VLSI techniques for power optimization and estimation of optimization. International Journal of Emerging Technology and Advanced Engineering, 2014, vol. 4, no. 9, pp. 351–355.
8. Durrani Y.A. Low-power integrated circuit design optimization approach. Technical Journal, UET, Taxila, 2016, vol. 21, pp. 32–42.
9. Hartstein A., Puzak T.R. Optimum power/ performance pipeline depth. Proc. 36th Int. Symposium on Microarchitecture. San Diego, USA, 2003. doi: 10.1109/MICRO.2003.1253188
10. Xu R., Melhem R., Mosse D. Energy-aware scheduling for streaming applications on chip multiprocessors. Proc. Real- Time Systems Symposium. Tucson, USA, 2007, pp. 25–36. doi: 10.1109/RTSS.2007.49
11. Sartori J., Ahrens B., Kumar R. Power balanced pipelines. IEEE International Symposium on High-Performance Comp Architecture. New Orleans, USA, 2012, pp. 261–272. doi: 10.1109/HPCA.2012.6169032
12. Kaeslin H. Digital Integrated Circuit Design. From VLSI Architectures to CMOS Fabrication. New York, Cambridge University Press, 2008, 845 p. doi: 10.1017/cbo9780511805172
13. Belyaev Y.V., Kostygov D.V., Lemko I.V., Mikhteeva A.A., Nevirkovets N.N. Design and testing of integrated circuit for micromechanical accelerometer. Proc. Problems of Advanced Micro- and Nanoelectronic Systems Development, 2018, no. 4, pp. 49–56. (in Russian) doi: 10.31114/2078-7707-2018-4-49-56
14. Belyaev Ya.V., Belogurov A.A., Bocharov A.N., Kostygov D.V., Lemko I.V., Mikhteeva A.A., Yakimova A.V., Nevirkovets N.N., Chernetskaya N.M. Development of a micromechanical accelerometer. Proc. 25th Int. Conf. on Integrated Navigation Systems. St. Petersburg, 2018, pp. 290–296. (in Russian)
15. Belous A.I., Murashko I.A., Syakersky V.S. Method for minimization of power consumption when designing CMOS VLIC. Tekhnologiya i Konstruirovanie v Elektronnoi Apparature, 2008, no. 2, pp. 39–44. (in Russian)
16. Panda P.R., Silpa B.V.N., Shrivastava B.V., Gummidipudi K. Power-Efficient System Design. Springer, 2006. 253 p. doi: 10.1007/978-1-4419-6388-8
17. Koshelev A.N., Salmin V.V., Generalov A.A., Bichkov D.S. The development of genetic algorithm with adaptive mutations to determine the global extremum function of n-variables. Internet Zhurnal Naukovedenie, 2016, vol. 8, no. 6, p. 32. (in Russian)
18. Kubař M., Jakovenko J. A powerful optimization tool for analog integrated circuits design. Radioengineering, 2013, vol. 22, no. 3, pp. 921–931.
